This application claims the benefit of priority from prior Japanese Patent Application P2001-323881, filed on Oct. 22, 2001, the contents of which are hereby incorporated by reference in their entirety.
The present invention relates to a semiconductor integrated circuit and method for operating the same, where the integrated circuit is supplied with a power supply voltage having a varying potential level.
In recent years, the miniaturization in large scale integration (LSI) fabrication processes has caused a lowering of the power supply voltage. For example, integrated circuit (IC) cards and subscribers identify module (SIM) cards (an IC card used for a portable information terminal) may have power supply voltages of 5V and 3V, and lately as low as 1.8V. Accordingly, such LSI cards must cope with a wide range of power supply voltages.
While such LSI cards may be designed to be compatible with power supply voltages of 5 V, 3 V, and 1.8 V, those cards generally operate optimally at one clock frequency for a given power supply voltage. When the power supply voltage of the LSI card is lowered, the operating speed of the LSI logic circuit generally decreases. If the operating speed goes too low due to the application of a power supply voltage lower than normal, the logic operation may become unstable, and thus cause the IC card to malfunction.
If the power supply voltage to the LSI then rises (e.g., when first applying the power supply or when recovering from a low power consumption mode or sleep mode), the internal logic circuit may become indeterminate. Again, this may cause the LSI card to become unstable. This is particularly likely when, before the power supply voltage begins to rise, the power supply voltage was low enough to cause a malfunction. In such situations, the circuit components of the IC card begin operating simultaneously before the IC card""s voltage regulator or constant voltage generation circuit has a chance to stabilize. The high amount of power required to simultaneously operate these components while the voltage regulator is attempting to stabilize to the new power supply voltage, causes the operation of the regulator to deteriorate.
Accordingly, there is a need for an IC card to be compatible with a power supply voltage having a varying potential level, and to prevent malfunctioning of the IC card when the potential level of the power supply changes.
In accordance with a first exemplary implementation of the invention, a semiconductor circuit is provided comprising a power supply voltage detection circuit to detect a potential level of an external power supply voltage and to output a detection signal dependent on a comparison of the potential level. A system control circuit detects the detection signal, outputs a status signal and an interrupt signal, and outputs a clock selection signal in response to an operation control signal. A outputs the operation control signal to the system control circuit in response to the status signal and the interrupt signal. A clock generation circuit generates a plurality of clock signals and a clock selection circuit selects one clock signal among the plurality of clock signals in response to the clock selection signal and outputs the one clock signal as a system clock signal.
According to a second exemplary implementation of the invention, a semiconductor circuit is provided, comprising a plurality of circuit components and a regulator to output a predetermined constant voltage as a regulated output voltage when supplied with a first external power supply voltage higher than the predetermined constant voltage. The regulator also outputs a second external power supply voltage as the regulated output voltage when supplied with the second external power supply voltage lower than the predetermined constant voltage. A power-on reset circuit outputs an internal reset signal which remains at a first logic level until the regulated output voltage exceeds a threshold voltage value lower than the second external power supply voltage and becomes a second logic level when the regulated output voltage exceeds the threshold value. A logic circuit computes a logical product of the internal reset signal and an external reset signal and outputs the logical product as a system reset signal. A CPU receives the system reset signal and outputs a low power consumption mode signal. A sequential activation circuit receives the internal reset signal and the low power consumption mode signal, and sequentially outputs enable signals respectively activating the plurality of circuit components. The enable signals are output at different times.
According to a third exemplary implementation of the invention, a semiconductor circuit is provided, comprising a plurality of circuit components and a regulator to output a predetermined constant voltage as a regulated output voltage when supplied with a first external power supply voltage higher than the predetermined constant voltage. The regulator also outputs a second external power supply voltage as the regulated output voltage when supplied with the second external power supply voltage lower than the predetermined constant voltage. A power-on reset circuit outputs an internal reset signal which remains at a first logic level until the regulated output voltage exceeds a threshold voltage value lower than the second external power supply voltage and becomes a second logic level when the regulated output voltage exceeds the threshold value. A logic circuit computes a logical product of the internal reset signal and an external reset signal and outputs the logical product as a system reset signal. A CPU receives the system reset signal and outputs a low power consumption mode signal. A sequential activation circuit receives the internal reset signal and the low power consumption mode signal, and sequentially outputs enable signals respectively activating the plurality of circuit components, wherein the enable signals are output at different times. A power supply voltage detection circuit detects a potential level of an external power supply voltage and outputs a comparison result of the external power supply voltage with a reference voltage as a detection signal. A system control circuit detects the detection signal, outputs a status signal and an interrupt signal, and outputs a clock selection signal in response to an operation control signal. A clock generation circuit generates a plurality of clock signals from a source clock signal. A clock selection circuit selects one clock signal among the plurality of clock signals in response to the clock selection signal and outputs the one clock signal as a system clock signal to the system control circuit, wherein the CPU further outputs the operation control signal to the system control circuit in response to the status signal and the interrupt signal.
According to a fourth exemplary implementation of the invention, a memory card is provided, comprising a card substrate and a semiconductor circuit mounted on the card substrate. The semiconductor circuit has a circuit to generate a plurality of clock signals from a source clock signal and a circuit to select one clock signal among the plurality of clock signals in accordance with a potential level of an external power supply voltage. An external terminal is mounted on the card substrate and a substrate wiring is provided on the card substrate to connect the external terminal and a pad on the semiconductor circuit. Further, a cover film is provided to cover the semiconductor circuit and the card substrate.
According to a fifth exemplary implementation of the invention, a memory card is provided, comprising a card substrate and a semiconductor circuit mounted on the card substrate. The semiconductor circuit has a plurality of circuit components, a regulator which increases an output voltage with time when supplied with an external power supply voltage lower than a normal constant output voltage, and a circuit which sequentially outputs enable signals of a first logic level at different times to sequentially activate the plurality of circuit components when an output of the regulator reaches a threshold value voltage lower than the external power supply voltage. An external terminal is mounted on the card substrate and a substrate wiring is provided on the card substrate to connect the external terminal and a pad on the semiconductor circuit. Further, a cover film is provided for covering the semiconductor circuit and the card substrate.
According to a sixth exemplary implementation of the invention, a method of operating a memory card is provided, comprising: generating a plurality of clock signals from a source clock signal; detecting a potential level of an external power supply voltage supplied from an external circuit and outputting a comparison result of the external power supply voltage with a reference voltage as a detection signal; detecting the detection signal and outputting a status signal and an interrupt signal; outputting an operation control signal in response to the status signal and the interrupt signal; outputting a clock selection signal in response to the operation control signal; and selecting one clock signal among the plurality of clock signals in response to the clock selection signal and outputting the one clock signal as a system clock signal.
According to a seventh exemplary implementation of the invention, a method of operating a memory card is provided, comprising: comparing an external power supply voltage supplied from an external circuit with a normal constant voltage; increasing a regulated output voltage to drive a plurality of circuit components on a semiconductor circuit when the external power supply voltage is lower than the normal constant voltage; and sequentially outputting enable signals at different times which respectively activate the plurality of circuit components when an output voltage of the regulated voltage reaches a specified threshold voltage value lower than the external power supply voltage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only, and should not be considered restrictive of the scope of the invention, as disclosed and claimed herein. Further, features and/or variations may be provided in addition to those set forth herein. For example, embodiments of the invention may be directed to various combinations and sub-combinations of the features described in the detailed description.